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--
-- Title       : Uhvati
-- Design      : Frejmer
-- Author      : Nenad Ljubicic
-- Company     : ETF
--
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--
-- File        : Uhvati.vhd
-- Generated   : Fri Jan  7 20:19:02 2005
-- From        : interface description file
-- By          : Itf2Vhdl ver. 1.20
--
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--
-- Description : prati v_in i kada se javi kombinacija 3ff, 0,0 na cetvrti takt salje jes=1
--
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library IEEE;
use IEEE.STD_LOGIC_1164.all;



entity Uhvati is
    port(
    V_IN   : in std_logic_vector (9 downto 0);
    clk       : in std_logic;
    res       : in std_logic;
    
    V_OU   : out std_logic_vector(8 downto 2);
    jes    : out std_logic := '0'
    );
end Uhvati;



architecture beh of Uhvati is 
    type states_trs is (PRVA, DRUGA, TRECA, CETVRTA, PETA);
    signal state : states_trs := PRVA;
begin

pp1: process (clk, res, v_in)is
    begin 
       if res='1' then
         state <= PRVA;
         jes <= '0';
         v_OU<="1111111";
       elsif rising_edge(clk) then 
         V_OU<=V_IN(8 downto 2);
         if V_IN = "1111111111" and state=PRVA then
          state <= DRUGA;           
          jes<='0';
         elsif V_IN = "0000000000" and state=DRUGA then
          state <= TRECA;
          jes<='0';
         elsif V_IN = "0000000000" and state=TRECA then
          state <= CETVRTA;
          jes<='0';
          
         elsif state=CETVRTA then
          jes <= '1';
          state <= PETA;
         elsif state=PETA then
          jes <= '0';
          state <= PRVA;
         else
          state <= PRVA;
         end if;
       end if;
    end process pp1;
    
end beh;