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--
-- Title       : Raspakivac
-- Design      : Frejmer
-- Author      : Nenad Ljubicic
-- Company     : ETF
--
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--
-- File        : Raspakivac.vhd
-- Generated   : Sat Jan  8 03:33:53 2005
-- From        : interface description file
-- By          : Itf2Vhdl ver. 1.20
--
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--
-- Description :  kada primi jes, postavlja err ako ima greske u XYZ na osnovu V_in
--
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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_arith.all;


entity Raspakivac is 
    port(
       clk     : in std_logic;
       V_IN  : in std_logic_vector(8 downto 2);
       jes     : in std_logic;
       res     : in std_logic;
       
       err   : out std_logic  :='0'
       );
end Raspakivac;

architecture beh of Raspakivac is
begin 
    
    pp1: process ( res,clk, jes)
    variable cnt_hbi:integer:=120;
    variable cnt_akt:integer:=900;

    begin 
       if res='1' then
         err <= '0';

       elsif rising_edge(clk) then   
          if jes='1' then
          if V_IN(5)=(V_IN(7) xor V_IN(6)) and V_IN(4)=(V_IN(8) xor V_IN(6)) and V_IN(3)=(V_IN(8) xor V_IN(7)) and V_IN(2)=(V_IN(8) xor V_IN(7) xor V_IN(6)) then
              err <= '0';
          else 
              err <= '1';    
          end if;  
         end if;
       end if;
       end process pp1;
end beh;