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--
-- Title       : Pratilica
-- Design      : Frejmer
-- Author      : Nenad Ljubicic
-- Company     : ETF
--
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--
-- File        : Pratilica.vhd
-- Generated   : Sun Jan  9 04:34:11 2005
-- From        : interface description file
-- By          : Itf2Vhdl ver. 1.20
--
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--
-- Description :  lovi pocetak slike i kada ga ulovi izbacuje sync=1 else sync=0    
-- zapravo lovi kombinaciju  h=0 f=1 ---> h=1 f=0
-- takodje postavlja kas, koji kada je SAV produzi h za 4 takta
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library IEEE;
use IEEE.STD_LOGIC_1164.all;



entity Pratilica is
    port(
       err   : in std_logic;
       v_in: in std_logic_vector(8 downto 6);
       clk   : in std_logic;
       res   : in std_logic;
       jes   : in std_logic;
       
       sync: out std_logic := '0' ;
       ho    : out std_logic :='1';
       f : out std_logic:='1';
       vo    : out std_logic:='1';
       kas   : out std_logic
       );
end Pratilica;

architecture beh of Pratilica is
    
    type states is (SYN0, ST1, SYN1);
    --type stanja is (PRVA, DRUGA, TRECA, CETVRTA); 
    type sta is (PRVA, DRUGA); 
    signal state : states := SYN0; 
    signal st : sta := PRVA;    
begin
    pp1: process (res, jes,clk, err)
    begin
       if res='1' or err='1' then
         sync<='0';
         state <= SYN0;
         st<=PRVA;
         f<= '1';
         ho<= '1';
         vo<= '1';
         kas<='0';
       elsif rising_edge(clk) then   
        if jes='1' then
         if v_in(6)='0' and v_in(8)='1' and state=SYN0 then
          state <= ST1;
          sync<='0';
         elsif  v_in(6)='1' and v_in(8)='0' and state=ST1 then
          state <= SYN1;
          sync <= '1';
          f<= v_in(8);
          ho<= v_in(6);
          vo<= v_in(7);
          kas<='0';
          if v_in(6)='1' and st=PRVA then
              st<=DRUGA;
              kas<='0';
          end if;
          if v_in(6)='0' and st=DRUGA then
              st<=PRVA;
              kas<='1';
          end if;
         
         elsif state=SYN1   then 
          f<= v_in(8);
          ho<= v_in(6);
          vo<= v_in(7);
          kas<='0';
          if v_in(6)='1' and st=PRVA then
              st<=DRUGA;
              kas<='0';
          end if;
          if v_in(6)='0' and st=DRUGA then
              st<=PRVA;
              kas<='1';
          end if;
         end if;
         end if;
         
       end if;
       
       
    end process pp1;
    
end beh;