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--
-- Title       : kasnilica
-- Design      : Frejmer
-- Author      : Nenad Ljubicic
-- Company     : ETF
--
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--
-- File        : Kasnilica.vhd
-- Generated   : Wed Jan 12 18:06:56 2005
-- From        : interface description file
-- By          : Itf2Vhdl ver. 1.20
--
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--
-- Description : pamti 4 takta h, kada je kas=1
--
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library IEEE;
use IEEE.STD_LOGIC_1164.all;



entity kasnilica is
    port(
       hi    : in std_logic;
       clk   : in std_logic;
       kas : in std_logic;
       
       ho    : out std_logic
       );

end kasnilica;

architecture beh of kasnilica is
signal cnt: integer:=3;

begin 
    
    pp2:process (clk, kas, hi)
    begin 
       if rising_edge(clk) then
         if kas='0'then
          ho<=hi;
          cnt<=3;
         elsif kas='1'and cnt>0 then  
          cnt<=cnt-1;
          ho<='1';
         else  
          ho<=hi;
         end if;
       end if;
         if kas='0' then
         ho<=hi;
         end if;
    end process pp2;   
       
end beh;