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--
-- Title       : Frejmer
-- Design      : Frejmer
-- Author      : Nenad Ljubicic
-- Company     : ETF
--
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--
-- File        : Frejmer.vhd
-- Generated   : Fri Jan  7 16:49:01 2005
-- From        : interface description file
-- By          : Itf2Vhdl ver. 1.20
--
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--
-- Description : Glavni uredjaj, koji povezuje ostale poduredjaje
--
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library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity Frejmer is 
    port(
       Rst      : in std_logic;
       Clock     : in std_logic;
       Video_in  : in std_logic_vector(9 downto 0);
       
       field     : out std_logic;
       v        : out std_logic;
       h        : out std_logic;
       y_c      : out std_logic;
       IN_SYNC     : out std_logic;
       line_number   : inout std_logic_vector(9 downto 0);
       pixel_number: inout std_logic_vector(9 downto 0)
       );
end Frejmer;

architecture behavioral of Frejmer is
    signal jeste   : std_logic:='0';
    signal erru       : std_logic :='0';
    signal hu2     : std_logic := '1';
    signal kasni   : std_logic :='0';
    signal V_UN       : std_logic_vector(8 downto 2);
    
begin
    uhvati: entity work.Uhvati(beh)
       port map(
         V_IN => Video_in,
         clk  => Clock,
         res   => rst,
         
         V_OU => V_UN(8 downto 2),
         jes => jeste
         );
         
    raspak: entity work.raspakivac(beh)
       port map(
         V_IN => V_UN(8 downto 2),
         clk  => Clock,
         res   => rst,
         jes => jeste,

         err  => erru
         );
    broj: entity work.brojalica(beh)
       port map(
         clk  => Clock,
         res   => rst,
         jes  => jeste,
         err   =>erru,
         v_in8 => V_UN(8 downto 8),
         v_in6 => V_UN(6 downto 6),      
                 
         l   =>  line_number,  
         p    =>  pixel_number, 
         y    => y_c
         );
    prat: entity work.pratilica(beh)
       port map(
         err  =>erru,
         v_in => V_UN(8 downto 6),
         clk  => Clock,
         res   => rst,
         jes   => jeste,
         
         sync =>IN_SYNC,
         f    => field, 
         ho   => hu2,
         kas => kasni,
         vo   => v 

         );
    kas: entity work.kasnilica(beh)
       port map(
         hi  => hu2,
         clk => Clock,
         kas  => kasni,
         
         ho   => h

       );         
         
end behavioral;