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--
-- Title       : brojac3
-- Design      : Frejmer
-- Author      : Nenad Ljubicic
-- Company     : ETF
--
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--
-- File        : Brojac3.vhd
-- Generated   : Thu Jan 20 01:43:26 2005
-- From        : interface description file
-- By          : Itf2Vhdl ver. 1.20
--
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--
-- Description : prati signale v_in i jes i na osnovu njih broji piksele i linije na ekranu
--
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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;


entity brojalica is 
    port(
       clk     : in std_logic;
       res     : in std_logic;
       err     : in std_logic;
       jes     : in std_logic;
       v_in8 : in std_logic_vector(8 downto 8);
       v_in6 : in std_logic_vector(6 downto 6);
       
       l     : inout std_logic_vector(9 downto 0):="0000000000"; 
       p     : inout std_logic_vector(9 downto 0):="1111111111";
       y     : out std_logic:='1'
       );    
end brojalica;


architecture beh of brojalica is  
    type states is (NoSYNC, H0F1, H1F0, SYN, SYNC1,SYNCm, NewLINE, NewSCREEN);
    type stanja is (NEPAR, PAR);
    signal state, next_state: states := NoSYNC;
    signal st : stanja:=NEPAR;
begin 

    
fsm_set_state: process (res,err, clk) is
    begin
        if res = '1' or err='1' then
            state <=NoSYNC;
        elsif rising_edge(clk) then
            state <= next_state;
        end if;
    end process fsm_set_state; 

    
fsm_set_next: process (state, jes, v_in8(8), v_in6(6)) is
    begin                       
        case (state) is
            when NoSYNC =>
                next_state <= NoSYNC;
                if v_in6(6)='0' and v_in8(8)='1' and jes='1' then
                    next_state <= H0F1;
                end if;
         when H0F1 =>
          next_state<=H0F1;
          if v_in6(6)='1' and v_in8(8)='0' and jes='1' then
              next_state<= H1F0;
          end if;
         when H1F0 =>
          next_state <= SYNCm;
            when SYN =>
          next_state <= SYNC1;
    
            when NewLINE =>
          next_state<=SYNCm;
         when NewSCREEN =>
          next_state <= SYNC1;
         when SYNC1 =>
          next_state<=SYNCm;
         when SYNCm =>
          next_state<=SYNC1;
        end case;
    end process fsm_set_next;    

    
    
pl: process (res,err, clk) is     
    begin
        if res = '1'or err='1' then
         p<="1111111111";
         l<="0000000000";
         st<=NEPAR;
         y<='1';
       elsif rising_edge(clk)then
           case (next_state) is
                when NoSYNC => 
              p<="1111111111";
              l<="0000000000";
          when H0F1 =>
              p<="1111111111";
              l<="0000000000";
          when H1F0 =>
              p<="0000000000";
              l<="0000000001";
              y<='0';
                when SYNC1 =>
              p<=p+1;
              y<='0';
              if v_in6(6)='1' and jes='1' then
                 l<=l+1;
                 P<="0000000000";
              end if;
              
              if v_in6(6)='1' and v_in8(8)='1' and jes='1' and st=NEPAR then
                 st<=PAR;
              end if;
              if v_in6(6)='1' and v_in8(8)='0' and jes='1' and st=PAR then
                 st<=NEPAR;
                 l<="0000000001";
                 p<="0000000000";
              end if;
              
          when SYNCm =>
              p<=p;
              y<='1';
                when SYN =>
              l<="0000000001";
              p<="0000000000";
          when NewLINE =>
              l<=l+1;
              p<="0000000000";
          when NewSCREEN =>
              l<="0000000001";
              p<="0000000000";
            end case;
       end if;
    
    end process pl;
    
end beh;